Job Description: Understanding the digital designs(Chip & IP); Designing chip Arch(Including Bus, Clock, IO_MUX, Power Domain, etc); Writing SDC and UPF; Running RTL and gate level simulation and regression; Coworking with Verification team, BE team and FPGA team;Job Qualification: Minmum of 5 years digital design experience; Familiar with design languages(verilog, System Verilog, SVA etc.); Familiar with Simulation & Debug Tools(VCS, Verdi, etc.); Familiar with Synthesis Tools(DC or RC.); Familiar with ASIC Design Flow; Scripting skills (perl, tcl, makefile, Python etc.) is a plus; Knowledge in low power design is a plus; Knowledge in STA is a plus;职能类别:集成电路IC设计/应用工程师关键字:设计工程师
关于灿芯半导体
灿芯半导体是一家提供一站式定制芯片及IP的高新技术企业,为客户提供从芯片架构设计到芯片成品的一站式服务,致力于为客户提供高价值、差异化的解决方案。
灿芯半导体的“YOU”系列IP和YouSiP(Silicon-Platform)解决方案,经过了完整的流片测试验证。其中YouSiP方案可以为系统公司、无厂半导体公司提供原型设计参考,从而快速赢得市场。
灿芯半导体成立于2008年,总部位于中国上海,为客户提供全方位的优质服务。
About Brite Semiconductor
Brite Semiconductor is a leading custom ASIC and IP provider, and mitted to provide flexible one-stop services from architecture design to chip delivery with high value and differentiated solutions.
Brite Semiconductor provides prehensive silicon proven “YOU” IP portfolio and YouSiP (Silicon-Platform) solution. YouSiP solution provides a prototype design reference for system house and fabless to speed up the time-to-market.
Founded in 2008, Brite Semiconductor is headquartered in Shanghai, China.